An end-to-end high-frequency trading platform - an FPGA fabric that runs on the NIC, vendor-neutral kernel-bypass networking, and a control plane written entirely in Rust.
Built on and interoperable with the standards that matter
Syscalls, context switches, and garbage collection add microseconds and jitter you can't budget for. HFTPlatform parses, risk-checks, and fires from inside the NIC - then hands everything else to a deterministic Rust control plane.
* Figures are illustrative reference targets and depend on card, feed, and configuration.
One coherent platform with clean abstraction boundaries - so you can swap silicon and retarget feeds without rewriting the parts that matter.
Feed decode, pre-trade risk, and order encode run inside the NIC fabric - never touching the kernel. Authored in Veryl or SystemVerilog and synthesized straight to your card.
A single API abstracts ef_vi, TCPDirect, Onload, and AF_XDP. Portability lives at the bypass layer - so you bind to silicon, not lock to it.
Feed handlers, OMS, risk, gateways, simulation, and backtesting - all in safe, GC-free Rust. The FPGA accelerator sits behind a trait boundary you can mock.
PTP / IEEE 1588 clock discipline as a platform primitive. Every tick and every order carries a nanosecond-accurate, hardware-sourced timestamp.
No syscalls, no allocation, no GC on the critical path. Latency is a budget you set - and bounded jitter you can prove with on-card telemetry.
The same strategy code runs in deterministic simulation, against historical replay, and in live trading. Reproduce any session, tick for tick.
The latency-critical path lives in fabric; everything else is Rust against an abstracted bypass API. Swap the card, keep the stack.
HFTPlatform standardizes on AMD/Xilinx Alveo FPGA-on-NIC silicon, tiered from baseline capture to sub-3-nanosecond transceiver latency - all behind the same bypass abstraction.
The current workhorse for production low-latency trading.
Sub-3 ns transceiver latency for the most aggressive strategies.
Entry tier for capture, development, and lower-rate feeds.
100GbE-class workloads where bandwidth leads latency.
Program against a clean Rust boundary, swap the FPGA backend for a software mock in tests, and stream per-stage telemetry from the card in production.
// The critical path lives in fabric; the rest of the // platform talks to it through one trait boundary. pub trait Accelerator { /// Submit a decoded book update; returns a /// fire decision evaluated in-fabric. fn on_tick(&self, tick: Tick) -> Decision; fn timestamp(&self) -> PtpNanos; } // Production: the X3522 fabric backend. impl Accelerator for FpgaFabric { /* … */ } // Tests & backtests: a deterministic mock, // same path, no card required. impl Accelerator for SimFabric { /* … */ } let engine = Engine::new(Transport::ef_vi("x3522:0")?); engine.run(strategy);
These are the ideas HFTPlatform refuses to compromise on.
Portability and longevity come from a clean bypass layer - ef_vi, TCPDirect, Onload, AF_XDP - not from betting the platform on one vendor's chip.
One memory-safe language across feeds, OMS, risk, gateways, sim, and tooling. The only exception is the fabric hot path, where the toolchain demands HDL - and we're honest about that.
A predictable tail beats a fast average. The hot path makes no syscalls and never allocates, so the worst case is a number you can budget.
Every layer is replaceable behind a trait. Mock the card and retarget the feed - without touching the parts that earn the latency.
Target your card and run the same code from backtest to production.